• Fight Patents abuse by EC authorities - Gegen Patentmißbrauch durch die EU-Behörden.

2.12 .. 14 vs previous versions:

• The numeric quasi-'local', directionally referrable labels numbered greater than "9" are now explicitely mentioned, single digit ones described as 'more efficiently implemented' than the others.
• The docs also explain about locally local labels, i.e. valid until the next global one, which should be terminated w. "$" instead of ":", at definition. - Just the common, GNU/FSF-style program 'developers' nonsense: In fact, AS (checked until 2.14.90) rejects those labels with some error message, e.g. "test-as.s:12: Warning: rest of line ignored; first ignored character is `2'".
• There is no means to specifying a <jmp> as "near" or "short", e.g. for compiler code or other purposes which rely on the known, constant code size. Some 'workaround' may be possible by declaring a global label any <jmp> to which apparently (i.e. un-documented!) gets assembled in the 'near' (long) variant.
• Note that there are several inconsistent addressing conventions
  re 8.10.11 (reversed operands order), 8.10.13 (derived mul opr's) [sowas kommt, wenn Dummheit sich mit Inkompetenz herausredet].
• In contrary to assertions in the GNU AS 'documentation' the GASP praeprocessor features are not incorporated in AS and, GASP, despite utterly broken (mainly by bad design and incompetent 'maintenance', if any), is certainly not 'obsolete' - since, whether those 'developers' realize or not, the real world does not change just by stubbornly repeated stupid statements...
• The 'GASP' was abandoned w. bu v2.13 which, was simply worthless because of its unuseable state and, could thus be considered 'obsolete', indeed.
• GNU/FSF distribution 'politics' seem to carefully hide any useable sort of 'documentation'; somewhat better readable docs (i.e. less un-readable than those 'info' pages) can be generated w. 'make dvi' and 'dvips' on the rsp. result.
  After <make> in the binutils/gas/doc directory, the html-files can be compiled with
  • makeinfo --force --html --no-split --no-headers --number-sections -I. -o as.html
• I do not know whether this is a fault in AS or, some somehow wanted feature or, something due to CPP praeprocessing of the rsp. source file. The line continuation character "\" is evaluated even if contained in a single line comment after "//". An example from the F4 sources (where I found that behaviour):

  		spush           //;\
  		incl TS         //; dup 1+ ndup -> 'nndup'
  		call Cndup      //;/

  where the 2nd line was not assembled! which, might be documented somewhere, carefully hidden...

8.10 80386 Dependent Features

The i386 version AS supports both the original Intel 386 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture extending the Intel architecture to 64-bits.

8.10.1 Options
8.10.2 AT&T Syntax versus Intel Syntax
8.10.3 Instruction Naming
8.10.4 Register Naming
8.10.5 Instruction Prefixes
8.10.6 Memory References
8.10.7 Handling of Jump Instructions
8.10.8 Floating Point
8.10.9 Intel's MMX and AMD's 3DNow! SIMD Operations
8.10.10 Writing 16-bit Code
8.10.12 Specifying CPU Architecture
8.10.11 AT&T Syntax bugs
8.10.13 Notes

8.10.1 Options

The i386 version of AS has a few machine dependent options:

--32 | --64

Select the word size, either 32 bits or 64 bits. Selecting 32-bit implies Intel i386 architecture, while 64-bit implies AMD x86-64 architecture.

These options are only available with the ELF object file format, and require that the necessary BFD support has been included (on a 32-bit platform you have to add --enable-64-bit-bfd to configure enable 64-bit usage and use x86-64 as target platform).

8.10.2 AT&T Syntax vs Intel Syntax

AT&T System V/386 assembler syntax is quite different from Intel syntax:

8.10.3 Instruction Naming

Instruction mnemonics are suffixed with one character modifiers which specify the size of operands.

The letters

`b', `w', `l' and `q'

Thus, `mov %ax,%bx' is equivalent to `movw %ax, %bx';
also, `mov $1,%bx' is equivalent to `movw $1, %bx'.

Almost all instructions have the same names in AT&T and Intel format [hp: intel 'dword' modifier to the operand and 'd' mnemonic affix replaced by 'l' affix to the mnemonic, re above]. There are a few exceptions:

The sign extend and zero extend instructions need a size to sign/zero extend from and a size to extend to. This is accomplished by using two instruction mnemonic suffixes in AT&T syntax. Base names for sign extend and zero extend are `movs...' and `movz...' in AT&T syntax (`movsx' and `movzx' in Intel syntax). The instruction mnemonic suffixes are tacked on to this base name, the from suffix before the to suffix. Thus, `movsbl %al, %edx' is AT&T syntax for "move sign extend from %al to %edx."

		bl			byte to long
		bw			byte to word
		wl			word to long
		bq			byte to quad (64-Bit)
		wq			byte to quad
		lq			byte to quad

The conversion instructions, Intel mnemonics compatibility; either naming may be used w. AS:

[hp'8/01] NOTE:
Probably not intentional, unless syntax mode ".att_syntax" or, ".intel_syntax" explicitely specified, the register names will be recognized letter case independently and don't require the leading % character. Which, for instance, won't compile the Linux kernel - fixed w/ ".att_syntax" in "entry.S". Register names do not collide with other, e.g. "macro", names while in .att_syntax mode; .intel_syntax behaviour wasn't tested but, apparently is case independent and, w/o that %.

8.10.4 Register Naming

Register operands are always (Quatsch! siehe oben) prefixed with `%'. The 80386 registers consist of

• the 8 32-bit registers
  `%eax' (the accumulator), `%ebx', `%ecx', `%edx', `%edi', `%esi', `%ebp' (the frame pointer), and `%esp' (the stack pointer).
• the 8 16-bit low-ends of these:
  `%ax', `%bx', `%cx', `%dx', `%di', `%si', `%bp', and `%sp'.
• the 8 8-bit registers:
  `%ah', `%al', `%bh', `%bl', `%ch', `%cl', `%dh', and `%dl' (These are the high-bytes and low-bytes of `%ax', `%bx', `%cx', and `%dx')
• the 6 section registers
  `%cs' (code section), `%ds' (data section), `%ss' (stack section), `%es', `%fs', and `%gs'.
• the 3 processor control registers
  `%cr0', `%cr2', and `%cr3'.
• the 6 debug registers
  `%db0', `%db1', `%db2', `%db3', `%db6', and `%db7'.
• the 2 test registers
  `%tr6' and `%tr7'.
• the 8 floating point register stack `%st' or equivalently
  `%st(0)', `%st(1)', `%st(2)', `%st(3)', `%st(4)', `%st(5)', `%st(6)', and `%st(7)'. These registers are overloaded by 8 MMX registers `%mm0', `%mm1', `%mm2', `%mm3', `%mm4', `%mm5', `%mm6' and `%mm7'.
• the 8 SSE registers registers
  `%xmm0', `%xmm1', `%xmm2', `%xmm3', `%xmm4', `%xmm5', `%xmm6' and `%xmm7'.

The AMD x86-64 architecture extends the register set by:

• enhancing the 8 32-bit registers to 64-bit:
  `%rax' (the accumulator), `%rbx', `%rcx', `%rdx', `%rdi', `%rsi', `%rbp' (the frame pointer), `%rsp' (the stack pointer)
• the 8 extended registers
  `%r8'--`%r15'.
• the 8 32-bit low ends of the extended registers:
  `%r8d'--`%r15d'
• the 8 16-bit low ends of the extended registers:
  `%r8w'--`%r15w'
• the 8 8-bit low ends of the extended registers:
  `%r8b'--`%r15b'
• the 4 8-bit registers:
  `%sil', `%dil', `%bpl', `%spl'.
• the 8 debug registers:
  `%db8'--`%db15'.
• the 8 SSE registers:
  `%xmm8'--`%xmm15'.

[hp'8/01] NOTE:
".intel_syntax" register names may be capitalized.

8.10.5 Instruction Prefixes

Instruction prefixes are used to modify the following instruction. They are used to repeat string instructions, to provide section overrides, to perform bus lock operations, and to change operand and address sizes. (Most instructions that normally operate on 32-bit operands will use 16-bit operands if the instruction has an "operand size" prefix.) Instruction prefixes are best written on the same line as the instruction they act upon. For example, the `scas' (scan string) instruction is repeated with:

  repne scas %es:(%edi),%al

Here is a list of instruction prefixes:

• Section override prefixes `cs', `ds', `ss', `es', `fs', `gs'. These are automatically added by specifying using the section:memory-operand form for memory references.
• Operand/Address size prefixes `data16' and `addr16' change 32-bit operands/addresses into 16-bit operands/addresses, while `data32' and `addr32' change 16-bit ones (in a .code16 section) into 32-bit operands/addresses. These prefixes must appear on the same line of code as the instruction they modify. For example, in a 16-bit .code16 section, you might write:

    addr32 jmpl *(%ebx)
  

• The bus lock prefix `lock' inhibits interrupts during execution of the instruction it precedes. (This is only valid with certain instructions; see a 80386 manual for details).
• The wait for coprocessor prefix `wait' waits for the coprocessor to complete the current instruction. This should never be needed for the 80386/80387 combination.
• The `rep', `repe', and `repne' prefixes are added to string instructions to make them repeat `%ecx' times (`%cx' times if the current address size is 16-bits).
• The `rex' family of prefixes is used by x86-64 to encode extensions to i386 instruction set. The `rex' prefix has four bits -- an operand size overwrite (64) used to change operand size from 32-bit to 64-bit and X, Y and Z extensions bits used to extend the register set.
• You may write the `rex' prefixes directly. The `rex64xyz' instruction emits `rex' prefix with all the bits set. By omitting the 64, x, y or z you may write other prefixes as well. Normally, there is no need to write the prefixes explicitly, since gas will automatically generate them based on the instruction operands.

8.10.6 Memory References

An Intel syntax indirect memory reference of the form

  section:[base + index*scale + disp]

  section:disp(base, index, scale)

where base and index are the optional 32-bit base and index registers, disp is the optional displacement, and scale, taking the values 1, 2, 4, and 8, multiplies index to calculate the address of the operand. If no scale is specified, scale is taken to be 1. section specifies the optional section register for the memory operand, and may override the default section register (see a 80386 manual for section register defaults). Note that section overrides in AT&T syntax must be preceded by a `%'. If you specify a section override which coincides with the default section register, AS does not output any section register override prefixes to assemble the given instruction. Thus, section overrides can be specified to emphasize which section register is used for a given memory operand.

Here are some examples of Intel and AT&T style memory references:

AT&T: `-4(%ebp)', Intel: `[ebp - 4]'

base is `%ebp'; disp is `-4'. section is missing, and the default section is used (`%ss' for addressing with `%ebp' as the base register). index, scale are both missing.

AT&T: `foo(,%eax,4)', Intel: `[foo + eax*4]'

index is `%eax' (scaled by a scale 4); disp is `foo'. All other fields are missing. The section register here defaults to `%ds'.

AT&T: `foo(,1)'; Intel `[foo]'

This uses the value pointed to by `foo' as a memory operand. Note that base and index are both missing, but there is only one `,'. This is a syntactic exception.

AT&T: `%gs:foo'; Intel `gs:foo'

This selects the contents of the variable `foo' with section register section being `%gs'.

Absolute (as opposed to PC relative) call and jump operands must be prefixed with `*'. If no `*' is specified, AS always chooses PC relative addressing for jump/call labels.

Any instruction that has a memory operand, but no register operand, must specify its size (byte, word, long, or quadruple) with an instruction mnemonic suffix (`b', `w', `l' or `q', respectively).

The x86-64 architecture adds an RIP (instruction pointer relative) addressing. This addressing mode is specified by using `rip' as a base register. Only constant offsets are valid. For example:

AT&T: `1234(%rip)', Intel: `[rip + 1234]'

Points to the address 1234 bytes past the end of the current instruction.

AT&T: `symbol(%rip)', Intel: `[rip + symbol]'

Points to the symbol in RIP relative way, this is shorter than the default absolute addressing.

Other addressing modes remain unchanged in x86-64 architecture, except registers used are 64-bit instead of 32-bit.

8.10.7 Handling of Jump Instructions

Jump instructions are always optimized to use the smallest possible displacements. This is accomplished by using byte (8-bit) displacement jumps whenever the target is sufficiently close. If a byte displacement is insufficient a long displacement is used. We do not support word (16-bit) displacement jumps in 32-bit mode (i.e. prefixing the jump instruction with the `data16' instruction prefix), since the 80386 insists upon masking `%eip' to 16 bits after the word displacement is added. (See also see section 8.10.12 Specifying CPU Architecture)

Note that the `jcxz', `jecxz', `loop', `loopz', `loope', `loopnz' and `loopne' instructions only come in byte displacements, so that if you use these instructions (gcc does not use them) you may get an error message (and incorrect code). The AT&T 80386 assembler tries to get around this problem by expanding `jcxz foo' to

      jcxz cx_zero
      jmp cx_nonzero
cx_zero: jmp foo
cx_nonzero:

8.10.8 Floating Point

All 80387 floating point types except packed BCD are supported. (BCD support may be added without much difficulty). These data types are 16-, 32-, and 64- bit integers, and single (32-bit), double (64-bit), and extended (80-bit) precision floating point. Each supported type has an instruction mnemonic suffix and a constructor associated with it. Instruction mnemonic suffixes specify the operand's data type. Constructors build these data types into memory.

• Floating point constructors are `.float' or `.single', `.double', and `.tfloat' for 32-, 64-, and 80-bit formats. These correspond to instruction mnemonic suffixes `s', `l', and `t'. `t' stands for 80-bit (ten byte) real. The 80387 only supports this format via the `fldt' (load 80-bit real to stack top) and `fstpt' (store 80-bit real and pop stack) instructions.

• Integer constructors are `.word', `.long' or `.int', and `.quad' for the 16-, 32-, and 64-bit integer formats. The corresponding instruction mnemonic suffixes are `s' (single), `l' (long), and `q' (quad). As with the 80-bit real format, the 64-bit `q' format is only present in the `fildq' (load quad integer to stack top) and `fistpq' (store quad integer and pop stack) instructions.

Register to register operations should not use instruction mnemonic suffixes. `fstl %st, %st(1)' will give a warning, and be assembled as if you wrote `fst %st, %st(1)', since all register to register operations use 80-bit floating point operands. (Contrast this with `fstl %st, mem', which converts `%st' from 80-bit to 64-bit floating point format, then stores the result in the 4 byte location `mem')

8.10.9 Intel's MMX and AMD's 3DNow! SIMD Operations

AS supports Intel's MMX instruction set (SIMD instructions for integer data), available on Intel's Pentium MMX processors and Pentium II processors, AMD's K6 and K6-2 processors, Cyrix' M2 processor, and probably others. It also supports AMD's 3DNow! instruction set (SIMD instructions for 32-bit floating point data) available on AMD's K6-2 processor and possibly others in the future.

Currently, AS does not support Intel's floating point SIMD, Katmai (KNI).

The eight 64-bit MMX operands, also used by 3DNow!, are called `%mm0', `%mm1', ... `%mm7'. They contain eight 8-bit integers, four 16-bit integers, two 32-bit integers, one 64-bit integer, or two 32-bit floating point values. The MMX registers cannot be used at the same time as the floating point stack.

See Intel and AMD documentation, keeping in mind that the operand order in instructions is reversed from the Intel syntax.

8.10.10 Writing 16-bit Code

While AS normally writes only "pure" 32-bit i386 code or 64-bit x86-64 code depending on the default configuration, it also supports writing code to run in real mode or in 16-bit protected mode code segments. To do this, put a `.code16' or `.code16gcc' directive before the assembly language instructions to be run in 16-bit mode. You can switch AS back to writing normal 32-bit code with the `.code32' directive.

`.code16gcc' provides experimental support for generating 16-bit code from gcc, and differs from `.code16' in that `call', `ret', `enter', `leave', `push', `pop', `pusha', `popa', `pushf', and `popf' instructions default to 32-bit size. This is so that the stack pointer is manipulated in the same way over function calls, allowing access to function parameters at the same stack offsets as in 32-bit mode. `.code16gcc' also automatically adds address size prefixes where necessary to use the 32-bit addressing modes that gcc generates.

The code which AS generates in 16-bit mode will not necessarily run on a 16-bit pre-80386 processor. To write code that runs on such a processor, you must refrain from using any 32-bit constructs which require AS to output address or operand size prefixes.

Note that writing 16-bit code instructions by explicitly specifying a prefix or an instruction mnemonic suffix within a 32-bit code section generates different machine instructions than those generated for a 16-bit code segment. In a 32-bit code section, the following code generates the machine opcode bytes `66 6a 04', which pushes the value `4' onto the stack, decrementing `%esp' by 2.

  pushw $4

8.10.11 AT&T Syntax bugs

The UnixWare assembler, and probably other AT&T derived ix86 Unix assemblers, generate floating point instructions with reversed source and destination registers in certain cases. Unfortunately, gcc and possibly many other programs use this reversed syntax, so we're stuck with it.

For example

  fsub %st,%st(3)

8.10.11.1 "AT&T Syntax bugs" bugs [hp]

Addressing of the 64-bit shift operation:

shldl $count,source,destn

i.e. exactly, the at&t reversed syntax,

      att shldl $2,source,destn corresponds to intl shld destn,source,2 (nasm).

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8.10.12 Specifying CPU Architecture

 

AS may be told to assemble for a particular CPU architecture with the .arch cpu_type directive. This directive enables a warning when gas detects an instruction that is not supported on the CPU specified. The choices for cpu_type are:

`i8086'	`i186'	`i286'	`i386'
`i486'	`i586'	`i686'	`pentium'
`pentiumpro'	`pentium4'	`k6'	`athlon'
`sledgehammer'

Apart from the warning, there are only two other effects on AS operation; Firstly, if you specify a CPU other than `i486', then shift by one instructions such as `sarl $1, %eax' will automatically use a two byte opcode sequence. The larger three byte opcode sequence is used on the 486 (and when no architecture is specified) because it executes faster on the 486. Note that you can explicitly request the two byte opcode by writing `sarl %eax'. Secondly, if you specify `i8086', `i186', or `i286', and `.code16' or `.code16gcc' then byte offset conditional jumps will be promoted when necessary to a two instruction sequence consisting of a conditional jump of the opposite sense around an unconditional jump to the target.

Following the CPU architecture, you may specify `jumps' or `nojumps' to control automatic promotion of conditional jumps. `jumps' is the default, and enables jump promotion; All external jumps will be of the long variety, and file-local jumps will be promoted as necessary . Re section 8.10.7 Handling of Jump Instructions) `nojumps' leaves external conditional jumps as byte offset jumps, and warns about file-local conditional jumps that AS promotes. Unconditional jumps are treated as for `jumps'.
[hp: which, is another false, or incomlete, statement: Branches to '.global' labels get always compiled in the long variant! regardless of any other command, configuration or, GNU/FSF-'programmers' hope or whatsoever.]

For example

  .arch i8086,nojumps

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8.10.13 Notes

 
There is some trickery concerning the `mul' and `imul' instructions that deserves mention. The 16-, 32-, 64- and 128-bit expanding multiplies (base opcode `0xf6'; extension 4 for `mul' and 5 for `imul') can be output only in the one operand form. Thus, `imul %ebx, %eax' does not select the expanding multiply; the expanding multiply would clobber the `%edx' register, and this would confuse gcc output. Use `imul %ebx' to get the 64-bit product in `%edx:%eax'.

We have added a two operand form of `imul' when the first operand is an immediate mode expression and the second operand is a register. This is just a shorthand, so that, multiplying `%eax' by 69, for example, can be done with `imul $69, %eax' rather than `imul $69, %eax, %eax'.

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